As current designs close in on the physical limits of semiconductor based microprocessors, new problems, such as increased heat dissipation and power consumption, have prompted designers to consider alternatives to the traditional single die microprocessor. Accordingly, designers may employ parallel processing systems that include multiple microprocessors working in parallel in order to surpass the physical limits of a single processor system. However, such parallel systems with multiple processors place different sets of constraints on designers in comparison to single processor systems. For example, parallel processor based systems may have no centralized memory module and instead rely on linking memory modules at each node to create a global memory address space. These systems may have transactional memory support in order to facilitate concurrency control among the various memory modules. However, transactional memory support does not necessarily imply that the system has global cache or memory space coherence. Accordingly, it may be necessary to detect memory conflicts within the transactional memory system in shared memory systems that do not employ global memory coherence.